NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/programmer/6375

Internet Message Format | 1996-08-05 | 7.1 KB

Path: uvsq.fr!Newsmaster
From: Nicolas Pomarede <[e-mail]>
Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.games,alt.sys.amiga.demos,comp.sys.amiga.misc
Subject: Re: AB3D II beats Quake....
Date: 27 Mar 1996 12:36:08 GMT
Organization: Universite de Versailles/St Quentin en Yvelines - France
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[e-mail] (Fabio Bizzetti) wrote:
>
>Do you think that F1GP-II would still need a fast Pentium if it had a "decent"
>video chipset?

For this last one, we'll the Psygnosys/SONY new F1 game planned in june
for the PSX. This will certainly be a real kickass.

>
>At the time that the high-end AmigaPPC604 (although they said 603 for mid-end)
>arrives in 1997, I would compare the 604 with the 80686 that will be already
>*old*, and maybe in multiprocessing boards as standard for most tomorrow's PC.
>
>While the PPC620 (if not cancelled because, as IBM said, "it's not much faster
>than PPC604e") will be a 7.5 millions of (relatively) wasted transistors, if it
>can't outperform PPC604e so much. Which more improvements will the PPC630 have?
>At IBM they ran out of brain.

You seem to be quite reluctant with IBM, but don't forget that Motorola was
also involved in the PPC design (although I must reckon  it's mostly based
on IBM Power CPU).


>I see again a future for CISC: as the most expert of you know, the RISC haven't
>been invented yesterday, they are old as me. The RISC vs CISC "war" has always
>been combacted with RAM speed as main arm: when the RAM were relatively slow,
>the CISC was faster than RISC; when the RAM technology was faster than CPU's
>one, the RISC's were faster than CISC's. CPU technology has grown up a lot

I don't really agree with this one. Everything depends on the build-in cache
and the memory it uses. RISC has been designed to provide a more simplified
intruction set that should be easier and faster to decode.
Anyway, there's actually no RAM that can cope today with a 68 Mhz CPU
(at least not on a personnal computer). 68 Mhz means 14.7 ns RAM ; I don't
think you can have many megs of this kind of RAM. This kind of RAM is only
used in 8/32 K cache (or in VRAM), but in that case, both RISC and CISC
can use this RAM (SRAM), so the RAM don't make a big difference IMO.

>Advantages? 80x86 can contain upto 4 instruction codes into 32bit, while the
>PowerPC can contain only 1. This means that parallelization will allow 80x86
>to run 4 times faster than the fastest of PPC.

The problem is not the size of the opcode, it's the time needed to read it.
All modern CPU read opcode in one cycle, and since buses are 32 or 64 bits,
reading 8 bit is usually a waste of power.

One of the big problem of the Pentium and 680x0 is that the opcode are not
of the same size. 680x0 can have opcode of 2,4,8,10 bytes and x86 can even
have opcode of one byte (those compatible with 286).
On the other hand, RISC CPU have all their opcode with the same length
(usually 32 bits) ; in fact, while RISC was meant to have a Reduce Instruction
Set, this is today not that true. RISC is now mostly caracterized by the fact
that opcode all have the same size, which allow massive predecoding of the
instruction flow. RISC CPU can predecode up to 8 instructions in parallel,
because they know that every 32 bits there's a new intruction.

On CISC, it's  not possible, because opcode are not 32 bit aligned. This means
that before decoding intstruction i, you must decode instructions 0 to i-1.

This way RISC can also implement powerful branch prediction, which tend to
add no overhead whether the branch is taken or not.
Such prediction technology are not usable in CISC ; using them would mean
adding thousand of transistors that could be used to speed up other
instructions.


>
>We'll get soon BiCMOS technology for CPU's: 700Mhz, while the RAM will run at
>a speed hugely inferior. That day (in 1-2 years) having more concentrate
>programs (80x86 = upto 8 instructions every 64bit / PowerPC = upto 2) and
>being able to perform more things with each instruction ( = CISC philosophy)
>will outperform RISC's of lotsa times.

Again, I don't agree. The problem is not the size of the opcode, but the time
needed to execute it. Allowing 1 byte opcode means you won't be able
to do pipelining and predecoding of the instructions flow.
I don't think any chip firm today would go that way, ie using 1 byte
opcode.

For the 700 Mhz, I don't know if this will be reached in standard computer.
300/400 Mhz will certainly, but IMO, the next step in speeding up will be
having more than 1 CPU in parallel. From this point of view, I think the
BeBox is a good first attempt in this direction.


>Intel is not dumb, they said 3 years ago what I understood nowadays.
>Time for other people to understand it as well.
>
Intel is producing mass CPU, not clever CPU. I'm much more interested in
work and advices from HP, MIPS, ...


>The only thing that can allow a future to RISC is ~5ns RAM, which is unlikely
>to happen, indeed.
>
>So, we are back again.
>The AmigaPPC604 (note: expensive high-end model) is not standard yet, while the
>200Mhz PentiumPro is already available and going to be surpassed soon by the
>new much faster 80686/80786 "lotsa-Pentiums-into-a-chip" processors.
>

One of the big problem with the x86, is the poor number of register and the way
they have to be used. Really, having 32 or 64 regs (PPC) greatly helps
speeding up execution (as an  ASM supporter, I think you will agree on the
importance of the number of registers).

One of the proof to this is that a 68060/66 runs at the same speed as a P133
(this has been shown with some lightwave rendering, taking approx 12-13 min
on both machines).

For me, future will be be having many RISC CPU in parallel. This is already
done in SGI renderer, and I doubt they would do it if it wasn't worth.


From what I read in your previous post, you seem to be asm addicted and not
really pro-C. In fact, I was like you a few years ago ; I only swear by ASM;
I wanted to rewrite everything in asm, patch slow functions in the OS, etc...
But I changed my mind, I'm now also working on HPUX server, that run C code
quite fast. A general rule in computing says that 90% of the CPU power is spent
in only 10% of the whole code of a program. In that case, writting a portable
OS is possible (you could then make specific asm speed up on some platform).

I still enjoy coding in asm, but I'm also open to other language.
I agree with you on the point that next Amiga shouldn't only have some kind
of SVGA cards. For me, a dream machine would be a mixing of a fast PPC604
and sthg like the PSX or Saturn video hardware.

Also, you said PPC was the worst RISC, but on the other hand you would like
to see the 3DO M2 in an Amiga : do you know that the M2 is based on PPC603
and has its speed from it ?


----------------
Nicolas Pomarede
e-mail: [e-mail]